elismasilva commited on
Commit
4c4a1d7
·
1 Parent(s): cb6f2d9

enable CPU offloading

Browse files
Files changed (1) hide show
  1. app.py +2 -7
app.py CHANGED
@@ -1,6 +1,6 @@
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  import torch
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  import spaces
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- from diffusers import ControlNetUnionModel, AutoencoderKL, UNet2DConditionModel
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  import gradio as gr
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  from pipeline.mod_controlnet_tile_sr_sdxl import StableDiffusionXLControlNetTileSRPipeline
@@ -10,7 +10,6 @@ from pipeline.util import (
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  calculate_overlap,
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  create_hdr_effect,
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  progressive_upscale,
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- quantize_8bit,
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  select_scheduler,
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  )
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@@ -27,11 +26,7 @@ pipe = StableDiffusionXLControlNetTileSRPipeline.from_pretrained(
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  model_id, controlnet=controlnet, vae=vae, torch_dtype=torch.float16, use_safetensors=True, variant="fp16"
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  ).to(device)
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- # unet = UNet2DConditionModel.from_pretrained(model_id, subfolder="unet", variant="fp16", use_safetensors=True)
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- # quantize_8bit(unet) # << Enable this if you have limited VRAM
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- # pipe.unet = unet
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-
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- #pipe.enable_model_cpu_offload() # << Enable this if you have limited VRAM
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  pipe.enable_vae_tiling() # << Enable this if you have limited VRAM
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  pipe.enable_vae_slicing() # << Enable this if you have limited VRAM
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  import torch
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  import spaces
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+ from diffusers import ControlNetUnionModel, AutoencoderKL
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  import gradio as gr
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  from pipeline.mod_controlnet_tile_sr_sdxl import StableDiffusionXLControlNetTileSRPipeline
 
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  calculate_overlap,
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  create_hdr_effect,
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  progressive_upscale,
 
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  select_scheduler,
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  )
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  model_id, controlnet=controlnet, vae=vae, torch_dtype=torch.float16, use_safetensors=True, variant="fp16"
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  ).to(device)
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+ pipe.enable_model_cpu_offload() # << Enable this if you have limited VRAM
 
 
 
 
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  pipe.enable_vae_tiling() # << Enable this if you have limited VRAM
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  pipe.enable_vae_slicing() # << Enable this if you have limited VRAM
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